3D Integration for VLSI Systems
by Chuan Seng Tan (Nanyang Technological University, Singapore), Kuan-Neng Chen (National Chiao Tung University, Taiwan), Steven Koester (IBM, USA)
Hardback 377 pages 2011-09-30 Print ISBN: 9789814303811 eBook ISBN: 9789814303828 DOI: 10.4032/9789814303828
List price : $149.95
3D integration is expected to deliver performance improvement and functional enhancement in future integrated circuits and systems. This book covers a wide range of 3D integration topics authored by an impressive selection of experts. This is a great reference source for everyone following this promising technology.
Prof. L. Rafael Reif - Provost and Maseeh Professor of Emerging Technology, MIT, USA
Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV. There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration.
This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
|1||Chapter 1: 3D Integration Technology – Introduction and Overview|
Chuan Seng Tan, Kuan-Neng Chen and Steven J. Koester
|27||Chapter 2: A Systems Perspective on 3D Integration: What is 3D? And What is 3D Good For?|
Phil Emma and Eren Kursun
|43||Chapter 3: Wafer Bonding Techniques|
Bioh Kim, Thorsten Matthias, Viorel Dragoi, Markus Wimplinger and Paul Lindner
|71||Chapter 4: TSV Etching|
|91||Chapter 5: TSV Filling|
|121||Chapter 6: 3D Technology Platform: Temporary Bonding and Release|
|139||Chapter 7: 3D Technology Platform: Wafer Thinning, Stress Relief, and Thin Wafer Handling|
|153||Chapter 8: Advanced Die-to-Wafer 3D Integration Platform: Self-Assembly Technology|
Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka and Mitsumasa Koyanagi
|175||Chapter 9: Advanced Direct Bond Technology|
|205||Chapter 10: Surface Modification Bonding at Low Temperature for Three-Dimensional Hetero-Integration|
|231||Chapter 11: Through Silicon Via Implementation in CMOS Image Sensor Product|
Xavier Gagnard and Nicolas Hotellier
|263||Chapter 12: A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through- Silicon Via and Hybrid Cu-Adhesive Bonding|
|297||Chapter 13: Power Delivery in 3D IC Technology with a Stratum Having an Array of Monolithic DC-DC Point-of-Load (PoL) Converter Cells|
Ronald J. Gutman and Jian Sun
|313||Chapter 14: Thermal-Aware 3D IC Designs|
Xiaoxia Wu, Yuan Xie and Vijaykirshnan Narayanan
|335||Chapter 15: 3D IC Design Automation Considering Dynamic Power and Thermal Integrity|
Hao Yu and Xiwei Huang
|351||Chapter 16: Outlook|
Ya Lan Yang
Researchers and practicing engineers who are interested in enabling technology platforms (e.g., wafer bonding, TSV) and applications in the emerging field of 3D integration.
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