Metrology and Diagnostic Techniques for Nanoelectronics
by Zhiyong Ma (Intel Corporation, USA), David G. Seiler (National Institute of Standards and Technology, USA)
Hardback 1411 pages 2017-01-31 Print ISBN: 9789814745086
List price : $500.00
Nanoelectronics is changing the way how the world is communicated and is transforming our daily life. Continued Moore’s law scaling and miniaturization of low power semiconductor chips with ever increasing functionality in the past decade have been relentlessly driving research and development of new devices, materials, and process capabilities to meet performance, power and cost requirement. This book is designed to review the most recent work and results for selected important metrology and diagnostics topics being encountered in continuing Moore’s law scaling and product development. It is intended for a broad audience that is involved in all aspects of IC manufacturing and nanoelectronics from research to development to manufacturing. It can also serve as a reference book for those who study process and assembly technologies used in nanoelectronics or are involved in device testing, characterization, and diagnostic techniques.
The book is composed of twenty-five chapters divided into five parts covering characterization techniques and metrology for transistors, interconnects, defects, and emerging materials and devices, diagnostic methods and techniques for product debug and yield enhancement, and package fault isolation and defect imaging for 3D interconnects. The chapter authors are from academia, government labs, and industry, and have vast experiences and expertise in the topics presented.
About the Editors:
Zhiyong Ma has a bachelor’s degree in metallurgical engineering from Shanghai University of Technology, China; a master’s degree in materials engineering from Purdue University, Indiana; and a PhD in materials science and engineering from the University of Illinois, Urbana-Champaign. Dr. Ma worked at Digital Equipment Corporation as a senior process engineer in thin-film metallization and processing. He joined Intel’s Corporate Quality Network in 1995 as a senior process engineer. Currently, he is vice president of the Technology and Manufacturing Group and director of Technology Development and Manufacturing Labs at Intel, responsible for labs operations in support of silicon and assembly technology development and manufacturing, product fault diagnostics, and silicon and platform benchmarking, including strategic business planning, analytical technique development, metrology roadmaps, and fostering of innovation in lab metrology and diagnostic tool development. Dr. Ma holds 6 patents in underbump metallization, strained silicon transistors, secured fuse technology, and silicon diagnostic techniques and has published more than 25 refereed papers, as well as a book chapter on silicide technology. His research interests include thin-film kinetics, analytical techniques and metrology, and product fault diagnostics.
David G. Seiler received his PhD and MS in physics from Purdue University and a BS in physics from Case Western Reserve University, Ohio. In 2000, he received a Distinguished Alumni Award from Purdue University's School of Science for his contributions to and achievements in semiconductors. Dr. Seiler served as solid state physics program director in the Materials Research Division, National Science Foundation; spent a year's sabbatical at the MIT Francis Bitter National Magnet Laboratory; and was a regents’ professor of physics at the University of North Texas. He joined the National Institute of Standards and Technology (NIST) in 1988 and served as program analyst in the program office for the director of NIST and as materials technology group leader in the Engineering Physics Division. Currently, he is chief of the division, which provides technical leadership in measurement science research, development, and standards essential to improving US economic competitiveness for advanced manufacturing. Dr. Seiler has been the chairperson and proceedings editor of 13 international conferences or workshops. He is the co-editor and the co-author of a chapter in Semiconductors and Semimetals (1992, Vol. 36) and a co-author of a chapter in Handbook of Optics (1995). He is also a co-editor of journals and books containing the proceedings from 9 international conferences and workshops. His current research focus is on understanding and advancing the metrology and characterization measurements needed by the semiconductor industry. The results of his research have been disseminated in over 200 publications and 100 talks throughout the world.
Advanced undergraduate- and graduate-level students, postdocs, faculty members, industry R&D researchers, process and device engineers, semiconductor reliability and quality professionals . . . all those who are interested in learning the state of the art of what is involved in semiconductor R&D and manufacturing
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